{"id":225,"date":"2018-06-24T08:35:15","date_gmt":"2018-06-24T05:35:15","guid":{"rendered":"http:\/\/blog.aku.edu.tr\/ismailkoyuncu\/?page_id=225"},"modified":"2018-06-24T08:35:15","modified_gmt":"2018-06-24T05:35:15","slug":"fpga-tabanli-tasarimlar","status":"publish","type":"page","link":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/fpga-tabanli-tasarimlar\/","title":{"rendered":"FPGA ve VHDL"},"content":{"rendered":"

FPGA ve VHDL nedir?<\/h1>\n
\n

Alan\/alanda programlabilir kap\u0131 dizileri olarak t\u00fcrk\u00e7eye \u00e7evirebilece\u011fimiz FPGA \u00e7ipleri, ilk \u00fcretiminin ard\u0131ndan tekrar tekrar programlanabilme \u00f6zelli\u011fine sahip kullan\u0131c\u0131\/tasar\u0131mc\u0131 taraf\u0131ndan yap\u0131lan sistem tasar\u0131m\u0131na g\u00f6re yap\u0131s\u0131n\u0131n de\u011fi\u015ftirilebilece\u011fi t\u00fcmdevrelerdir. Di\u011fer platformlara g\u00f6re paralel \u00e7al\u0131\u015fma, h\u0131zl\u0131 ilk \u00fcretim ve y\u00fcksek performans gibi \u00f6zellikleriyle \u00f6n plana \u00e7\u0131kmaktad\u0131rlar. FPGA \u00e7ipleri Xilinx ve Altera (Intel) gibi \u00e7e\u015fitli firmalar taraf\u0131ndan \u00fcretilmektedir. Her \u00e7ip \u00fcreticisi \u00fcretmi\u015f oldu\u011fu \u00e7iplerin tasar\u0131m\u0131 i\u00e7in farkl\u0131 programlar geli\u015ftirmi\u015flerdir. Bu programlara Vivado (Xilinx) ve Quartus (Altera) \u00f6rnek olarak verilebilir. \u00c7iplerin tasar\u0131m\u0131 \u015fematik, Matlab HDL Coder ve baz\u0131 programlama dilleri ile ger\u00e7ekle\u015ftirilebilmektedir. Bu programlama dillerinden en \u00e7ok kullan\u0131lan Verilog ve VHDL dilleridir. FPGA \u00e7iplerinin h\u0131zl\u0131 bir \u015fekilde tasar\u0131mc\u0131 taraf\u0131ndan kullan\u0131labilmesi i\u00e7in farkl\u0131 firmalar taraf\u0131ndan FPGA Geli\u015ftirme Kartlar\u0131 \u00fcretilmi\u015ftir. \u00dclkemizde TRUE \u0130NOVASYON A.\u015e. taraf\u0131ndan \u00a0yerli olarak geli\u015ftirilen\u00a0 TRUE-ONE (https:\/\/trueinovasyon.com<\/a>) ve TRUE -ARTDAC7 FPGA kartlar\u0131 bunlara \u00f6rnek olarak verilebilece\u011fi gibi, AMD’nin \u00fcretmi\u015f oldu\u011fu ML605 (AMD),<\/a> Digilent (Digilent<\/a>) taraf\u0131ndan geli\u015ftirilen ZedBoard, Alinx ve Altera (Intel) gibi firmalar\u0131n \u00fcretmi\u015f oldu\u011fu fpga geli\u015ftirme kartlar\u0131 da bulunmaktad\u0131r. A\u015fa\u011f\u0131da konu ile ilgili baz\u0131 kaynaklar verilmi\u015ftir. \u201cDers Notlar\u0131\u201d men\u00fcler b\u00f6l\u00fcm\u00fcnde konu ile ilgili Vivado program\u0131nda haz\u0131rlanm\u0131\u015f baz\u0131 VHDL \u00f6rnekleri haz\u0131r proje olarak verilmi\u015ftir. Ayr\u0131ca Programlar men\u00fcs\u00fcnde Xilinx ISE Design Tools Program\u0131 i\u00e7in indirme linki verilmi\u015ftir.<\/p>\n<\/div>\n

00-) Xilinx ISE Nas\u0131l Kurulur?<\/p>\n

Xilinx ISE Webpack Kurulumu<\/a><\/p>\n

01-) Xilinx Vivado Nas\u0131l Kurulur?<\/p>\n

Xilinx Vivado Webpack Kurulumu<\/a><\/p>\n

FPGA ile Gomulu Sistem Tasar\u0131m\u0131na Giris<\/a><\/p>\n

Basys-2 Datasheed<\/a><\/p>\n

Basys-3 Datasheed<\/a><\/p>\n

Basys3_master<\/a><\/p>\n

FPGA Tabanl\u0131 Sinyal ve G\u00f6r\u00fcnt\u00fc \u0130\u015fleme Mehmet Ali \u00c7avu\u015flu_SIU2016_SUNUM-1<\/a><\/p>\n

01_ebook<\/a><\/p>\n

02_ebook<\/a><\/p>\n

03_ebook<\/a><\/p>\n

FPGA Deney Seti Kitap\u00e7\u0131\u011f\u0131<\/p>\n

A\u015fa\u011f\u0131da FPGA \u00e7iplerinde \u00e7al\u0131\u015fmak \u00fczere VHDL dilinde tasarlanm\u0131\u015f baz\u0131 uygulamalar i\u00e7in \u00f6rnek kodlar verilmi\u015ftir.<\/p>\n

1-) Xilinx ISE Nas\u0131l Kurulur?<\/p>\n

ise_setup_tutorial<\/a><\/p>\n

2-) FPGA \u00fczerinde VHDL dilinde Switch ile Led Yakma Uygulamas\u0131<\/p>\n

Xilinx ISE ile Led yakma Uygulamas\u0131<\/p>\n

Vivado Switch ile Led Yakma Uygulamas\u0131<\/p>\n

3-)\u00a0FPGA \u00fczerinde VHDL ile 2 Input And Gate Uygulamas\u0131<\/p>\n

Xilinx ISE \u0130ki Giri\u015fli And Kap\u0131s\u0131 Uygulamas\u0131<\/p>\n

VIVADO \u0130ki Giri\u015fli And Kap\u0131s\u0131 Uygulamas\u0131<\/p>\n

4-)\u00a0FPGA \u00fczerinde VHDL ile 3 Input NOR Gate Uygulamas\u0131<\/p>\n

Xilinx ISE 3 Giri\u015fli NOR Kap\u0131s\u0131 Uygulamas\u0131<\/p>\n

Vivado 3 Giri\u015fli NOR Kap\u0131s\u0131 Uygulamas\u0131<\/p>\n

5-) FPGA \u00fczerinde VHDL ile Half Adder Uygulamas\u0131<\/p>\n

Xilinx ISE Yar\u0131m Toplay\u0131c\u0131<\/p>\n

Vivado Yar\u0131m Toplay\u0131c\u0131<\/p>\n

Half Adder-Full Adder Circuits in VHDL\/Yar\u0131m ve Tam Toplay\u0131c\u0131 Devreleri<\/p>\n

 <\/p>\n

Full Adder in VHDL on FPGA\/FPGA-tabanl\u0131 Tam Toplay\u0131c\u0131<\/p>\n

 <\/p>\n

Adder Circuits in VHDL\/Toplay\u0131c\u0131 Devreleri<\/p>\n

4-bit Adder in VHDL on FPGA \/FPGA-tabanl\u0131 4-bit Toplay\u0131c\u0131<\/p>\n

Adder_n-bit_generic in VHDL on FPGA<\/p>\n

 <\/p>\n

Counter Circuits in VHDL\/Say\u0131c\u0131 Devreleri<\/p>\n

Down_counter_4-bit in VHDL on FPGA\/FPGA-tabanl\u0131 A\u015fa\u011f\u0131 Say\u0131c\u0131_4-bit<\/p>\n

Up_counter_2-bit in VHDL\u00a0on FPGA\/FPGA-tabanl\u0131 2-bit Yukar\u0131 Say\u0131c\u0131<\/p>\n

Up_down_counter_8-bit in VHDL on FPGA\/FPGA-tabanl\u0131 8-bit Yukar\u0131 A\u015fa\u011f\u0131 Say\u0131c\u0131<\/p>\n

Up_down_counter_n-bit_generic in VHDL on FPGA\/FPGA-tabanl\u0131 n-bit Yukar\u0131\/A\u015fa\u011f\u0131 Say\u0131c\u0131<\/p>\n

 <\/p>\n

Multiplexer Circuits in VHDL\/Veri Se\u00e7ici Devreleri<\/p>\n

Multiplexer_4X1 in VHDL\u00a0on FPGA\/FPGA-tabanl\u0131 4X1 Veri_Secici<\/p>\n

 <\/p>\n

Multiplier Circuits in VHDL\/\u00c7arp\u0131c\u0131 Devreleri<\/p>\n

Multiplier_5-bit in VHDL on FPGA\/FPGA-tabanl\u0131 5-bit \u00c7arp\u0131c\u0131<\/p>\n

Multiplier_n-bit in VHDL on FPGA\/FPGA-tabanl\u0131 n-bit \u00c7arp\u0131c\u0131<\/p>\n

 <\/p>\n

Register Circuits in VHDL\/Kaydedici Devreleri<\/p>\n

Register_1-bit in VHDL on FPGA\/FPGA-tabanl\u0131 1-bit Kaydedici<\/p>\n

Register_4-bit in VHDL on FPGA\/FPGA-tabanl\u0131 4-bit Kaydedici<\/p>\n

Register_n-bit_generic in VHDL on FPGA\/FPGA-tabanl\u0131 n-bit Kaydedici<\/p>\n

 <\/p>\n

Subtractor Circuits in VHDL\/\u00c7\u0131kar\u0131c\u0131 Devreleri<\/p>\n

Subtractor_10-bit in VHDL on FPGA\/FPGA-tabanl\u0131 10-bit \u00c7\u0131kar\u0131c\u0131<\/p>\n

Subtractor_n-bit_generic in VHDL on FPGA\/FPGA-tabanl\u0131 n-bit \u00c7\u0131kar\u0131c\u0131<\/p>\n

 <\/p>\n

Di\u011fer Devreler<\/p>\n

Floating Point Number \u00d6rnek Devre Modeli_1<\/a><\/p>\n

Floating Point Number \u00d6rnek Devre Modeli_2<\/a><\/p>\n

Floating Point Number \u00d6rnek Devre Modeli_3<\/a><\/p>\n

Floating Point Number \u00d6rnek Devre Modeli_4<\/a><\/p>\n

Floating Point Number \u00d6rnek Devre Modeli_5<\/a><\/p>\n

 <\/p>\n

FPGA \u00e7ipi \u00fczerinde VHDL ile \u00c7e\u015fitli Genel Uygulamalar ve \u0130lgili Dosyalar A\u015fa\u011f\u0131daki Linklerde verilmi\u015ftir.<\/p>\n

1-) U01_sayici_devre<\/p>\n

2-) U02_step_motor<\/p>\n

3-) U03_LCD<\/p>\n

4-) U04_orneksel_sayisal_cevirici<\/p>\n

5-) U05_vga<\/p>\n

6-) U06_DC_motor<\/p>\n

7-) U07_kronometre<\/p>\n

\ud83d\ude0e U08_8x8_MATRIX<\/p>\n

9-) U09_klavye_kontrollu_LCD<\/p>\n

10-) U10_elektronik_zar<\/p>\n

11-) U11_rs232<\/p>\n

12-) U12_ram<\/p>\n

13-) U13_hesap_makinasi<\/p>\n

14-) U14_ultrasonik_lojik<\/p>\n

15-) U15_nokia_lcd_fpga<\/p>\n

16-) U16_keypad_lojik<\/p>\n

 \t\t<\/p>\n","protected":false},"excerpt":{"rendered":"

FPGA ve VHDL nedir? Alan\/alanda programlabilir kap\u0131 dizileri olarak t\u00fcrk\u00e7eye \u00e7evirebilece\u011fimiz FPGA \u00e7ipleri, ilk \u00fcretiminin ard\u0131ndan tekrar tekrar programlanabilme \u00f6zelli\u011fine sahip kullan\u0131c\u0131\/tasar\u0131mc\u0131 taraf\u0131ndan yap\u0131lan sistem tasar\u0131m\u0131na g\u00f6re yap\u0131s\u0131n\u0131n de\u011fi\u015ftirilebilece\u011fi t\u00fcmdevrelerdir. Di\u011fer platformlara g\u00f6re paralel \u00e7al\u0131\u015fma, h\u0131zl\u0131 ilk \u00fcretim ve y\u00fcksek performans gibi \u00f6zellikleriyle \u00f6n plana \u00e7\u0131kmaktad\u0131rlar. FPGA \u00e7ipleri Xilinx ve Altera (Intel) gibi \u00e7e\u015fitli firmalar … <\/p>\n

Devam\u0131n\u0131 oku<\/a><\/p>\n","protected":false},"author":3,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-225","page","type-page","status-publish","hentry","nodate","item-wrap"],"_links":{"self":[{"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/pages\/225","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/comments?post=225"}],"version-history":[{"count":0,"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/pages\/225\/revisions"}],"wp:attachment":[{"href":"https:\/\/blog.aku.edu.tr\/ismailkoyuncu\/wp-json\/wp\/v2\/media?parent=225"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}